In the field of integrated circuit fabrication technology, there is a continuing need to design circuit components having a high packing density. To achieve high packing density, circuit components are typically Fabricated in vertically distributed layers of material. For example, the need to fabricate circuits having a high packing density has lead to wide-spread use of multi-layered electrical interconnects. Furthermore, advances in thin-film technology have enabled designers to fabricate MOS transistors in thin-film layers overlying active substrate devices. For example, thin-film load transistors are commonly used in SRAM memory cells in order to increase the packing density, and to provide increased integration levels in memory devices, microprocessors, microcontrollers, and the like.
Although thin-film transistors provide a means of increasing the packing density of an integrated circuit, when the transistor channel length is fabricated below one micron, erratic variation in operating performance is observed. The non-uniformity of operating performance from one transistor to the next is, in part, related to the physical characteristics of the materials used in fabrication. Thin-film transistors are typically formed in polycrystalline silicon. Polycrystalline silicon is a granular material having a grain size distribution ranging from about 0.1 to 1.0 micron. The grains within the polycrystalline silicon can function as trapping sites for impurities. The impurities cause localized changes in the electrical characteristics of polycrystalline silicon.
A localized high population of trapping sites in the channel region of a thin-film transistor can lead to erratic transistor performance. For example, when the gate length of a thin-film transistor approaches the size of the grains found in polycrystalline silicon, variations in the on and off current of a thin-film transistor are observed. Additionally, the variance in electrical conductivity causes a random variation in the threshold voltage of thin-film transistors fabricated to the same nominal gate dimensions.
To further compound the problem of grain-induced variance in electrical conductivity, uncontrolled dopant diffusion along the grain boundaries of polycrystalline silicon also occurs. The diffusion of dopants preferentially takes place along the grain boundaries of the polycrystalline silicon. When the gate length of a thin-film transistor is substantially the same as the size of the polycrystalline grains, uncontrolled diffusion of dopants within the channel region causes a further variance in electrical conductivity. Foe example, the lateral diffusion of dopants into the channel region of a thin-film transistor increases the current leakage through the transistor when the transistor is in the off-state.
One solution to nonuniform electrical conductivity in thin-film transistors having a gate length in the sub-micron range, is to form the thin-film transistor in a very thin layer of polycrystalline silicon. By reducing the thickness of the polycrystalline silicon, less variation in grain size distribution can be expected. However, while the fabrication of the channel region in a polycrystalline silicon layer having a thickness of less than 500 angstroms, improves the on and off current performance, the reduced thickness also increases the series resistance of the transistor. Although greater uniformity in performance is attained, the overall performance level in the thin-film transistors is reduced. Accordingly, further development in the design of thin-film transistors is necessary to fully realize the potential advantage of high packing densities possible with their incorporation into integrated circuit devices.